The density of transistors in integrated circuits has been following Moore's law since its conception. (See, e.g., Reference 5). However, as the size of transistors approaches the size of a single atom, the laws of quantum physics play an increasingly dominant role in computer architectures, making it difficult for this trend to continue much longer. Despite this, the prospect of utilizing quantum mechanical phenomena in information processing offers an opportunity to increase the computational power of computers beyond what is known to be possible on even the most ideal classical computer. (See, e.g., References 5 and 6). Much like the classical computer depends on the robustness of the transistor, functional quantum computers can require an on-chip physical component with reproducible properties that can be incorporated into large scale structures.
One of the leading candidates for the quantum analog of the transistor is the gate-defined, semiconductor, quantum dot. (See, e.g., References 8 and 9). The spin state of an electron trapped in a quantum dot can be a beneficial physical system for storing quantum information. (See, e.g., References 10 and 12). Silicon (“Si”) in particular, with its weak hyperfine fields, small spin-orbit coupling and lack of piezoelectric electron-phonon coupling, forms a “semiconductor vacuum” for spin states (see, e.g., Reference 13), and supports seconds-long electron spin coherence times. (See, e.g., Reference 14). However, the fabrication of reliable and scalable Si-based quantum dots has proved challenging. Independent of the need for a pure spin environment, quantum dots should have reproducible electrical properties for scaling. The large effective mass of electrons in Si, along with the typically lower mobilities of Si two-dimensional (“2D”) electron gases, makes the fabrication of tightly confined, few-electron, quantum dots with reproducible properties difficult. (See, e.g., Reference 15).
Early quantum dot gate architectures were fabricated on doped Gallium Arsenide/Aluminum Gallium Arsenide (“GaAs/AlGaAs”) substrates in which conduction electrons are provided by a global dopant layer, and can be confined to the GaAs/AlGaAs quantum well (“QW”) interface forming a two-dimensional electron gas (“2DEG”). In these doped structures, by default, the 2DEG is filled with conduction electrons. Therefore, gate designs attempted to isolate a single conduction electron by fabricating gate electrodes in a corral pattern that could potentially create a circular barrier by applying negative voltages on the gates to deplete the 2DEG directly beneath the gates. (See, e.g., Reference 1). Devices utilizing this type of gate pattern have been referred to as depletion mode devices.
Depletion mode devices have been very successful in demonstrating the criteria for quantum computation (see, e.g., Reference 2), and are still in widespread use throughout the quantum dot community. However, there are major drawbacks to depletion mode devices with respect to control of the confinement potential and scaling. The gate patterns in depletion mode devices likely have the most control over the electrostatic potential surrounding the dot, rather than having direct control over the region of space where the electron wavefunction resides. This inability to control the electron wavefunction has led to a large variety of depletion mode gate designs, most of which do not provide a straightforward path for scaling to tens or hundreds of quantum dots.
The use of the quantum dots in quantum computing architectures generally depends on the ability to control the confinement potential of the quantum dot, and more specifically the ability to control the physically relevant parameters of the quantum dot, (e.g., tunnel coupling and the electrochemical potential). However, depletion mode devices have very limited control over the confinement potential. Simulations of the depletion mode quantum dot devices have shown that the resulting confinement potential can be much smaller than the gate dimensions. (See e.g., Reference 3). Because of such a situation, neighboring gates usually have a similar effect on the dot's tunnel couplings and electrochemical potential, and often it's not possible in depletion mode devices to tune the tunnel couplings and electrochemical potential to the desired values without going to such extreme voltages that dielectric breakdown occurs in the device. (See, e.g., Reference 4).
Quantum computing architectures require that the gate pattern be scalable. This can imply that the gate pattern must consist of unit cells that can be repeated over and over to create larger arrays. Most of the gate patterns which have been developed thus far do not consist of unit cells, and the gate patterns for double and triple quantum dots do not resemble the gate patterns for single quantum dots. This can make it unclear how to take existing gate patterns and extend (e.g., scale) them to tens or hundreds of quantum dots.
Thus, it may be beneficial to provide an exemplary semiconductor quantum dot device, which can overcome at least some of the deficiencies described herein above.